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AIC3843 current-mode pwm controller a n alog integrations corporation si-soft research center ds-3843p-02 010405 3a1, no.1, li-hsin rd. i , science park , hsinchu 300, taiw an , r.o.c. tel: 886-3-5772500 fax: 886-3 - 5772 510 www.analog.com .tw 1 features low start-up current (300 a typic a l) internal precision reference. 500khz current-mode operation. pulse-by-pulse current limiting. automatic feed-forward compensation. optimized for off-line and dc/dc converters. under - voltage lockout with hysteresis. double pulse suppression. high current totem pole output. applications ac/dc off-line converter. dc/dc off-line converter. description the aic3 843 control ic p r ovide s the f eatures that are nece s sary to impleme n t off-line or dc/ dc conv erter fixed - fre quen cy cu rre n t-mod e schem es with a minimu m numbe r of external com pon ents. this i n tegr ated ci rcuits feature s an und er-voltage lo ckout (uvlo ) with app roxi- mately 300 a start-u p cu rre nt, a pre c isi o n referen c e tri mmed for a c curacy at the error amplifier in pu t, high gain erro r amplifie r, current sen s in g com parator, logi c to in sure latche d ope ration, a nd a totem - pol e output stage d e s ig n e d to s o urc e or s i nk h i gh pe ak c u r r e n t . the output stage, suitab le for driving the n- channel mosfets, is low in the off state. typical application circuit m1 c3 1000p c2 300pf c6 300p rs 0. 33 r2 20k r4 7. 5k r1 10 r5 390 r3 51k c5 0. 1 f c4 2. 2nf c7 1nf + c1 47 f com p vr ef a i c 3843 i n duct or feed bac k sig n al vc c 7 6 5 3 4 8 1 2 vc c outp ut rt / c t gnd isen se vfb current mode pwm control circuit
AIC3843 ordering information ex am ple: aic3 843c st r in so - 8 p a c k age & t apin g & re el pac k ing t y pe ( cn is not a v ai la ble in t ape & r e e l pac k i ng t y p e .) aic3 843 pst r in so - 8 le ad f r e e p a c k age & t api ng & re el pac k ing t y pe pac king t y p e t r : t ape & r e e l tb : tu b e pac k a g i ng t ype n: pl a s t i c dip s: sm all o u t l in e c: comm erci al p: l e a d f r e e co mm er cial a i c 38 4 3 xxxx pin configu r at ion di p - 8 ( cn&pn) so - 8 ( c s&ps) to p vi e w outp ut vr ef vc c gnd is en se vfb rt / c t com p 1 3 4 2 8 6 5 7 absolute maximum ratings supply voltage (l ow impe dan ce sou r ce ) 30v supply voltage (i cc <30 m a ) self limiting output cu rre n t 1a output energ y (cap acitive load ) 5 j analog inp u ts (pins 2, 3) -0. 3 v ~ +6. 3 v erro r amp o u tput sink cu rre nt 10ma power dissipation at ta 25 c dip pack age 1w soic pac k age 725mw ope r ating te mperature ra nge -40 c ~ 85 c jun c tion t e m perature ran g e 125 c storage t e m perature ran g e ?65 c ~ 150 c lead t e mpe r ature (s olde ri ng 10 se c) 260 c note 1: all v o ltages are w i th respect to pin 5. all currents are positiv e into the specified terminal. note 2: absolute maximum ratings are those v a lues bey ond w h ich the life of a dev i ce may be impaired. 2
AIC3843 test circuit r5 4. 7k a r4 100k e rror a m p. ad ju st r7 4. 7k isen se ad ju st q2 2n2222 r6 10k r3 5k rt c2 0. 1 f outp ut a i c 3843 ct ground s1 vc c v ref r1 1k 1w c1 0. 1 f comp vr ef vfb vc c ise n se gnd rt / c t outp ut 3
AIC3843 electrical characteristics {v cc = 15v (see note 3), -40 q c Q t a Q 85 q c, unless otherw ise specified.} (note 6 ) p a r a m e t e r s c o n d i t i o n s m i n . t y p . m a x . units reference section output voltage i o = 1 m a 4 . 9 5 5 . 1 v line regulation v cc =12v to 25v 5 2 0 m v load regulation i o = 1 ma to 20ma 5 2 5 m v temperature coefficient of output voltage 0 . 2 0 . 4 mv/ q c output noise voltage f =10hz to 10khz 5 0 p v output voltage long term drift after 1000h at t a =25 q c 5 2 5 m v short circuit output current - 3 0 - 8 5 - 1 8 0 ma oscillator section oscillator frequency (see note 4) 4 7 5 2 5 7 k h z frequency change with supply voltage vcc=12v to 25v 0.2 1 % frequency change with temperature ta= t low to thigh 5 % peak-to-peak amplitude at rt/ct 1 . 7 v error amplifier section feedback input voltage comp at 2 . 5 v 2 . 4 2 2 . 5 0 2 . 5 8 v input bias current - 0 . 3 - 2 p a open-loop voltage amplification v o = 2 v to 4v 6 5 9 0 d b gain-bandwidth product 0 . 7 1 m h z supply voltage rejection ratio v cc =12v to 25v 6 0 7 0 d b output sink current v fb at 2.7v, comp at 1.1v 2 1 0 m a output source current v fb at 2.3v, comp at 5v - 0 . 5 - 1 m a high-level output voltage v fb at 2.3v, r l =15k : to gnd 5 6 . 2 v low-level output voltage v fb at 2.7v, r l =15 : to vref 0 . 8 1 . 1 v 4
AIC3843 electrical characteristics (continued) p a r a m e t e r s c o n d i t i o n s m i n . t y p . m a x . units current sense section voltage amplification see note 4 and 5 2.85 3 3.15 v/v current sense comparator threshold comp at 5v, see note 4 0.9 1 1.1 v supply voltage rejection ratio v cc =12v to 25v, see note 4 7 0 d b input bias current -2 -10 output section i source =20ma 1 3 1 3 . 5 v high-level output voltage i source =200ma 1 2 1 3 . 4 v i sink =20ma 0 . 1 0 . 4 v low-level output voltage i sink =200ma 1 . 5 2 . 2 v rise time c l =1nf 5 0 1 5 0 n s fall time c l =1nf 5 0 1 5 0 n s under voltage lockout section start threshold voltage 7.8 8.4 9.0 v 7 . 0 7 . 6 8 . 2 v minimum operating voltage after s t a r t - u p pulse-width-m odulator section maximum duty cycle 95 96 100 % minimum duty cycle 0 % supply voltage start-up current 0.3 0.5 ma operating supply current v fb and i sense at 0v 12 17 ma limiting voltage i cc =25ma 3 0 3 4 v 5
AIC3843 note: 3: adjust vcc above the star t threshold before setting it to 15v. 4. these parameters are measured at the tr ip point of the latch with vfb at 0v. 5. voltage amplification is measured between isen se and comp with the input changing from 0v to 0.8v. 6. specifications are production tested at ta = 25 c. specifications over the -40 c to 85 c operating temperature range are assured by design, characte rization and correlation with statistical quality controls (sqc). typical performance characteristics oscillator section 4 5 r t c t r t /c t v re f gn d fo r r t > 5 k , f 8 t t c * r 72 . 1 d e ad ti me v s ct ( r t > 5k ? ) td ( s) ct ( n f ) 11 0 0. 3 1 3 1 0 0 0 10 30 t i m i ng resist a n c e v s . frequen cy rt ( k ? ) fr eq u enc y ( h z ) 10 2 10 3 10 4 10 5 10 6 3 10 10 0 ct = 1 00 nf 47 nf 2 2nf 10 nf 2. 2n f 1 . 0nf 4. 7nf 30 fig. 1-1 fig. 1-2 fig. 1-3 s a tu ra t i o n v o l t a g e - (v ) out p ut cur r e nt , s o ur c e or s i nk - ( a ) 0. 01 0. 1 1 0 1 2 3 5 6 7 s o u r c e sa t (v c c - v oh) sin k s a t ( v o l ) vc c= 1 5 v ta = + 2 5 s o l i d line ta = - 5 5 da s h l i ne 10 100 1k 10k 10 0k 1 m -20 0 20 40 60 80 phase (degr e e ) v o lt a ge g a i n (db ) f r eque ncy (h z ) -20 0 -15 0 -10 0 -50 0 f i g. 1-4 output saturation ch a r acteristics f i g. 1-5 error amplifie r open-loop f r equency response 6
AIC3843 7 8 6 r s vc c gnd v ref 5v / 50m a com p outp ut vfb isen se rt / c t vr e f goo d logi c uv lo pw m lat c h os c zd 34v current s ens e c o m p arat or in te r n a l bia s e rror a m p. d1 z1 1v d2 2r 2. 50v s/r 5v re f q2 q1 7 5 4 1 2 3 + - r t pin 1: comp - this pin is t he error am plifier output and is made avai lable for loop compensation. pin 2: vfb - this i s the inverting in pu t of the erro r amplifier. it is norm a lly co nne cted to the swit chin g po we r su pply o u tput through a resistor divider. pin 3: isense - a voltage proportional to indu ctor cu rrent is co nne cte d to this input. the pwm use s this informat ion to terminate the output switch conduction. pin 4: rt/ct - the o scill ato r frequ en cy and maximum output duty cycl e are pro g ram m ed by con nect - ing re si stor r t to v ref and cap a cit o r c t to ground. it is feasibl e to operate whe n f Q 500khz. pin 5: gnd - this pin is the combin ed control circuitry and power ground. pin 6: output- this o u t put dire ctly drive s the gate of a power m o sfet. peak current s up to 1a are sourced and sunk by this pin. pin 7: vcc - this pin is the positive supply of the control ic. pin 8: vref - this is the referenc e output. it provid es cha r gin g cu rrent for cap a cito r ct throu gh re s i stor rt.
AIC3843 application information under voltage lockout there a r e t w o sepa rate u nde r voltage locko u t com parators inco rp orate d to mak e s u re that the ic is fully function al befo r e the outp u t stage i s enabl ed. one is for power sup p ly voltage (vcc) and the oth e r is fo r refere nce outp u t voltage (vref ) . each has a bu ilt in hystere s i s to prevent erratic o u tpu t behavio r whe n thei r resp ective thre shol ds are cro s sed. f o r vc c c o mp ar a t o r the uppe r and lo we r threshold s are 8.4v and 7.6v, re spe c tively. the large hy steresi s and low sta r t up curre n t (0.3ma) of the aic384 3 make it ideally suit ed in off-line converte r ap pl ication s whe r e efficie n t bootstra p startu p techni que s are req u ire d . a 34v zen e r is con n e c ted a s a shunt reg u lator fro m vcc to ground. its purpose is to prote c t the i c from exce ssive volta g e that ca n occur during system start-up. reference output the 5.0v refere nce outpu t is trimmed to 2.0% tolera nce at t a =25 c. it supplie s cha r gi ng cu rre nt to th e oscill ator timing ca pa citor and i s cap able of providing curre n t in exce ss of 20ma for po we ring addition al co ntrol sy stem circuitry. in ca se of ov erlo ad, the re feren c e i s sh ort-circuit protected at about 85ma. error amplifier a fully c o mpensated error amplifier is provided with invertin g input and output externally acce ssi ble. the non -inve r ting input is i n tern ally biased at 2.5 v . the co nve r ter o u tput vo ltage i s usu a lly divided down an d conn e c ted to the inverting input. the outp u t of the erro r a m plifier is acce ssi bl e for external lo op comp en sa tion, with an offset at two dio de d r ops ( ? 1.4v) and divid ed by three, before conn ected to the inverting inpu t of the cu rre nt sen s e comp arato r . this g uarant ees tha t no drive pulse appears at the output (pin 6). oscillator the oscillator frequency can be programmed throu gh the setting of timing com p o nents r t and c t . c a pac ito r c t is ch arg ed from th e 5.0v referen c e out put throug h r t to abo ut 2.8v and discha rg ed to abo ut 1.2v by the intern a l discha rg e cu rrent. wh en c t i s di scha rged th e output (pin 6 ) must be in the low state, thu s pro d u c ing a cont rolle d amou nt of output deadtim e. no te that many values of r t and c t can pro d u c e the sam e fre quen cy but o n ly on e com b ination will yield a specific output deadtime at a given frequency. current sense comparator and pwm latch the output switch of aic3 843 is initiate d by the oscillator and terminated when the pea k indu ctor current rea c h e s the thresh old level establi s h ed b y the error a m plifier outp u t (pin 1). the aic38 4 3 is ope rate d at a curre n t mode sin c e the ind u cto r cu rrent is monito red cycle - by - cycle and decides the duty cycle. the indu ctor current is converte d to a voltag e by insertin g the groun d refere nce d sen s e re sist o r r s in serie s with the sou r ce of outpu t swit ch m1. this volta g e is monito re d by the cu rre nt sense input (pin 3 ) and is com pared to a level derive d from the error amplifie r o u tput. in the norm a l operating con d ition s the pea k indu ctor cu rrent is cont rol l ed by the v o ltage a t 8
AIC3843 pin 1 where i vp i n 1 1 4 v 3r s pk = ? () . pwm latch is used to ensure that only a singl e pulse app ears at the output durin g a n y given oscillator cycl e. howeve r, a narrow spi k e on the leadin g ed g e of the cu rre nt wavefo rm ca n usu a lly be ob se rved an d may cau s e t he po we r supply to ex hibit an in stability when the output is tightly loaded. output sw itch the aic3 8 43 contain s a sin g le to tem-pol e output stag e that was spe c ifically de sig ned f o r dire ct drive of power m o sfet. if a n y unde r voltage locko u t is detected , internal circuitry wil l kee p the o u t put swit ch i n a si nki n g cu rre nt mode, no external pull down resistor is needed. error amp configuration z f 1 2 + - v fb co mp 0. 5 m a 2. 50 v er ro r amp c a n so u r c e or si nk u p to 0. 5m a z i fig. 2 under-voltage lockout 7 v on v of f a i c 3843 8. 4v 7. 6v 17m a 500 a v off v on v cc i cc duri ng under-vol t age l o ck out , t h e out p u t dri v er i s bi a s ed t o s i n k m i nor a m ount s of c u rrent . p i n 6 s houl d be s hunt e d t o ground w i t h a bl eeder res i s t or t o prevent ac t i vat i ng t h e pow er s w i t c h w i t h ext r an eous l e a k age c u rrent s. fi g. 3-1 fi g. 3-2 9
AIC3843 10 current sense circuit r c r s i s 2r r 1v gn d c u rre nt se ns e comp error am p c u rrent sens e c o m p arat or peak c u rrent (i s ) is d e t e rm ined by t he f o rm ula a s m al l r c f i l t er m a y be requi red t o s u p p re s s sw it c h t r a n s i en t s . i sm a x | 1. 0v r s fig. 4 open-loop laboratory fixture 1 2 3 4 5 6 7 8 co m p v fb i se n s e r t /c t v re f v cc ou t p u t gn d a 4. 7k 1k er r o r am p ad j u st 4. 7k i se n s e ad j u st 1 00k 2n 22 22 r1 ai c 3 843 0. 1 p f 0. 1 p f 1k 1w vr ef vc c ou t p u t gn d 5k c t h i g h pe a k c u r r e n t s as s o c i a t ed w i t h c a pa c i t i v e l o a d s ne c e s s i t a t e c a r e f u l g r ou n d i n g t e c h n i qu es . t i m i ng a n d by pa s s c a p a c i t o r s s h o u ld b e c o n n ec t e d c l o s e t o p i n 5 in a s i n g l e p o in t gr o u nd . t h e t r a n s i s t o r a n d 5 k p o t e nt io m e t e r a r e u s ed t o s a m p l e t h e o s c i ll at or w a v e f o r m an d app l y an ad ju s t a b le ra m p to p in 3 . fig. 5
AIC3843 11 open-loop laboratory fixture 8 3 1 v re f i sen se 1k 330 ? 50 0 sh ut d o w n t o current sen se re si st o r shu t do w n co m p fig. 6-1 f i g. 6- 2 s h ut dow n of the a i c 3 843 c a n be acc o m p lis hed by tw o m e t h ods ; eit h e r rais e pin 3 above 1v or pull pin 1 be l o w a v o lt age tw o- diode dr op s a bov e gr ound . e i ther m e t h o d causes t h e o u t p ut of the p w m c o m p arator to be high (re f e r to bloc k diagr am ) . t he p w m latc h is reset dom inant so t h a t t h e o u t p ut w i ll rem a in low unti l t h e n e x t c l ock cy c l e af ter t h e shut do w n c o ndit i on at pin 1 and / o r 3 is re m o ved. i n on e e x a m ple, a n e x ter nally latc h ed s hut d o w n m a y be ac com p lis h ed by adding an s c r , w h ic h w i ll b e re s e t b y cy c ling v c c below the low e r u v l o thre s hold. a t this point t h e r e f e rence t u r n s of f, allow i n g the s c r to reset. offline fly back regulator uf n833 22 ? 1 2 3 4 5 6 7 8 va r o vm6 8 11 7 v a c c1 25 0 f 25 0v r2 56 k 2w r 12 2w 4. 7k c9 3 300pf 6 00v d4 1n36 13 np t1 n5 n12 n1 2 nc d6 us d94 5 c1 0 4 700 f 10 v c1 1 4 700 f 10 v + 5v co m +1 2 v 12 v co m - 12v c1 2 2200 f 16 v c13 2200 f 16 v d7 u f s 1 0 02 d8 u es1 00 2 r1 1 2. 7k 2w c8 680p f 16 v d5 1n36 13 q1 r7 r1 3 10 k c7 4 70pf r8 1k us d1 120 r10 0.55 ? 1w d4 1n361 3 d2 1n36 12 c3 22 f c2 100 f 25v c4 47 f 25v r9 68 ? 3w r3 20 k r4 4. 7 k r5 150 k c14 100 pf r6 10 k c6 0.00 2 2 f c5 0. 01 f a i c3 843 1. i n p u t v o l t age 9 5 v a c to 1 30v a ( 5 0h z/60hz) 2. li ne i s o l at i o n 3 750v 3. s w i t ch i n g fr equ ency 4 0 kh z 4. e f fi ci e n cy @ ful l load 7 0 % 5 . ou t p ut v o l t a ge: a . + 5 v , 5 % ; 1a to 4 a l o a d r i ppl e vol t a ge: 5 0 m v p - p m a x b . + 1 2v , 3 % ; 0 . 1a to 0. 3 a l o a d r i ppl e vol t a ge: 1 00m v p - p m a x c . -1 2v , 3 % ; 0 . 1 a to 0.3a l o ad r i ppl e vol t a ge: 1 00m v p - p m a x p o w e r s uppl y s p eci fi catio n s l1 10 h r1 5 ? 1w fig. 7
AIC3843 12 slope compensation ai c 3 8 4 3 0. 1 f r2 c r sen se a f r a c t i o n of t h e os c i l l at or r a m p c a n b e r e si st i v e l y su m m e d w i t h t h e cu r r e n t se n s e s i gn al t o p r o v ed s l o p e c o m p e n s a t i on f o r c o n v er t e r s r e q u i r i n g d u t y c y c l e s ov e r 5 0 % n o te th a t c a p a c i to r , c f o r m s a f i l t e r w i th r 2 to s u p p r e ss t h e l e a d i n g e d g e s w i t ch sp i k e s . v re f i sen se c t r t /c t i sen se r1 r t 8 4 3 fig. 8 physical dimensions 8 lead plastic so h l d e h e c b a1 0.5 0 0. 25 0. 40 0 1. 27 8 1.2 7 bs c 4. 80 5. 80 3. 80 0. 33 0. 19 0. 10 5.0 0 6. 20 4. 00 0.5 1 0.2 5 0.2 5 s y m b o l a sop-8 mill imet ers 1. 35 mi n . 1. 75 max. a bas e m etal wi th pla t ing a1 b c d e aa h e h x 45 s e e view b l vi ew b 0.25 se at i n g pl an e g aug e p l an e
AIC3843 g auge plane 0. 38 a a2 eb ea e1 d e b d 9. 01 e d1 7. 62 0. 13 c b2 b 0. 20 1. 1 4 0. 36 10 .16 8. 26 0. 3 5 1.7 8 0. 5 6 mi ll imet ers min. s y m b o l a1 a2 a 0. 38 2. 92 max. 4. 95 5. 3 3 di p- 8 8 lead plastic dip 13 note: information p r ovided b y aic is be lieved to be accurate an d reli able. ho w e ver , w e cannot assume r e sponsibility f o r use of an y circuitry o t her t h an circuitr y entir ely embodi ed in an aic p r oduct ; nor fo r an y infr ingement of pat ents or othe r rig h ts of thir d parties that may result from its use. we reserve the right to change the circuitry and spec ifications w i thout notice. life support policy : aic does not authorize an y ai c product fo r us e in life support devices and/or sy st ems. life support device s or s y stems are d e vices or sy stem s w h ich, (i) a r e i n tended for su rg ical imp l ant into the bod y o r (ii) support or sustain life, a nd w h ose failure to perform, w hen pr operl y used in ac cordance w i th in structions for use provided in the labeling, can be r easonabl y expected to result in a significant injury to the user. a1 l d1 a b2 a e c 2 . 54 bsc e l eb ea 2. 92 7. 6 2 b s c 3. 8 1 10 .92 e1 6. 1 0 7. 1 1

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